This disclosure relates to clock signal generators for electronic systems and circuits, and particularly, a duty cycle generator and method of operation for adjusting and setting duty cycle of a signal for timing operations with less jitter and increased accuracy.
Clocking signals used in most electronic systems provide the heart beat and pulse lines for correct operation. High speed applications such as SerDes (Serial/Deserializer) and DDR (double data rate) transmitter links sending data on both edges of a reference clock rely highly on its duty cycle. Duty cycle distortions in such applications impact timing margin and performance affecting eye closure.
Usually duty cycle distortions occur due to incoming clock duty cycle variations, systematic PFET vs. NFET process mismatch that affect threshold voltages, drive strength, etc, and local PFET vs. NFET device mismatch. They can also be altered by the processing circuit's architecture. For example, embedded PLLs (phase locked loops) used for clock generation could use LFSR (Linear Feedback Shift Register) divider architectures primarily chosen due to programmability and high speed operation. However the duty cycle (pulse duration) creation mechanics could not necessarily give a 50% output (which can vary based on the divide value chosen). Clock propagation circuits such as DLLs (Delay Locked loops), Delay lines, Phase Rotators, I/O drivers in-turn could cause additional static distortion (across process, voltage and temperature (PVT) ranges that the circuits are specified to run at) to the incoming variation, making the net outgoing static duty cycle variation worse.